1. Technical Field
This disclosure relates to integrated circuits, and more particularly, to various method and apparatus embodiments for testing memories implemented in integrated circuits.
2. Description of the Related Art
Memory arrays on integrated circuits may be tested using different test mechanisms. One such mechanism is a memory built-in self-test (MBIST). Memory testing using this mechanism is implemented with a controller that is coupled to the memory array (or arrays) to be tested. The controller may generate various types of test patterns in which data is written to and read from the memory, wherein the reading of data may be used to verify whether or not the memory passes a given test. The controller may convey signals to the memory over address lines, data lines, and control lines (e.g., read enable, write enable, bank enable), and may receive signals over data lines as well. Thus, the controller may test the functionality of the entire memory array, including address and control circuitry, as well as testing individual memory cells. The controller may also provide signals to devices external to the integrated circuit in which the memory array is implemented in order to indicate the results of a particular test.
An MBIST controller (sometimes referred to as an MBIST engine) may be implemented externally to the memory (or memories) to be tested. Additionally, an IC configured with an MBIST engine may also include comparison circuitry external to the memory (or memories) to be tested. After test data patterns are written into the memory under test, data may be read from the written locations and compared to an expected value (i.e. the value that is written into the memory). Thus, in addition to writing data into the memory under test itself, an MBIST engine may also provide the same data to comparison circuitry to verify that the correct data is read from the memory.